The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a nonvolatile semiconductor memory device in which data can be electrically written and erased.
A nonvolatile semiconductor memory device has an advantage in that data cannot be erased even if power is turned off, and for this reason a demand for the memory device has sharply increased in these years. A flash memory, which is a nonvolatile semiconductor memory device capable of performing electrical batch erasure of data, differs from a byte-type non-volatile semiconductor memory device using two transistors and can constitute a memory cell comprising a single transistor. As a result, it is possible to reduce the size of the memory cell, and it is expected that the flash memory will substitute for a large-capacity magnetic disk.
Among such flash memories, a NAND type EEPROM is known, in particular, as being advantageous for attaining higher integration density. The NAND type EEPROM has a structure to be described below. For example, a plurality of memory cells are arranged in a column direction, and the source and drain of adjacent two of the cells are series-connected in succession. Thereby, a unit cell group (or a NAND cell unit) in which a plurality of cells are series-connected is constituted. The unit cell group is connected to a bit line as one unit.
On the other hand, the memory cell has a stacked gate structure in which a floating gate, which normally functions as a charge accumulation layer, and a control gate are stacked on each other. The memory cells are integrally formed in a matrix format in a p-type substrate or a p-type well formed in an n-type substrate. A drain side of the NAND cell unit is connected to a bit line via a selection gate. A source side of the NAND cell unit is connected to a source line (a reference potential line) via a selection gate. The control gates of the memory cells are connected to word lines arranged in the row direction.
When data is to be written in the NAND cell unit, the threshold values of the transistors of all memory cells in the NAND cell unit are, at first, set on the negative side ("1" level) by an erasure operation. Then, data is written in succession from the memory cell remotest from the bit line. Specifically, a high voltage is applied to the control gate of a selected memory cell. Thereby, an intermediate potential is applied to the control gates of the memory cells located on the bit line side and the selection gates. In this state, 0V or an intermediate potential is applied to the bit line according to write data.
If 0V is applied to the bit line, electrons appearing in the channel region between the source and drain regions are injected into the floating gate by an FN tunnel phenomenon. As a result, the threshold value of the transistor of the selected memory cell is shifted to the positive side and "0" data is written. Inversely, when the intermediate potential is applied to the bit line, no electrons are injected in the floating gate and the threshold value of the transistor remains on the negative side. The selected memory cell is set in the data "1" state.
When the written data is to be erased, all control gates are set at 0V and the bit line and source line are set in the floating state. For example, in a case where the memory cell is formed in a p-type well in an n-type substrate, a high voltage is applied to each of the p-type well, n-type substrate and selection gate. Thereby, in all memory cells, electrons in the floating gates are drawn out to the p-type well by the FN tunnel phenomenon. As a result, the threshold of the transistor of each memory cell is shifted to the negative side. In other words, data is erased in all memory cells at a time.
In general, in the NAND cell unit, when the data is written or erased, it is necessary to supply an effectively high electric field between the floating gate and substrate when the high voltage is applied to the control gate or the p-type well and n-type substrate. Thereby the electrons can sufficiently be injected/ejected into/from the floating gate. In this case, the magnitude of the electric field between the floating gate and the substrate is determined by a coupling ratio, i.e. a ratio between the capacitance of the insulating film between the control gate and floating gate and the capacitance of the insulating film between the floating gate and the substrate.
Specifically, at the time of data write, the voltage to be applied between the floating gate and substrate is determined by a value obtained by multiplying the voltage applied to the control gate by the coupling ratio. At the time of data erase, the voltage to be applied between the floating gate and substrate is determined by a value obtained by multiplying the voltage applied to the substrate by the coupling ratio. In the case of a NAND cell unit having a coupling ratio of, e.g. 0.65 and including an insulating film which is formed of a silicon oxide film with a thickness of 0.01 .mu.m between the floating gate and substrate, in order to fully inject or eject electrons into or from the floating gate by the FN tunnel phenomenon, it is necessary to apply a high bias of 20V to the control gate or the p-type well and n-type substrate and to supply an electric field of about 13 MV/cm to the insulating film between the floating gate and substrate. In this case, the relationship between the coupling ratio and the bias at the time of data write or erase is exactly applicable to NOR type memory cells, etc. in which data is written by means of substrate hot electrons.
In the above-described nonvolatile semiconductor memory device having the stacked gate structure comprising the floating gate and control gate, when data is written/erased in/from the memory cell, specific peripheral circuits for controlling the write/erase operations are driven by a high voltage applied to the control gate or the p-type well and n-type substrate. Thus, part of the transistors constituting the peripheral circuits need to comprise high-breakdown voltage transistors having a high insulation breakdown voltage and, in particular, a high drain breakdown voltage under a channel region.
In the prior art, there is a technique wherein MOS transistors constituting part of the peripheral circuits are formed on the semiconductor substrate along with transistors of memory cells. Then, oxidation of a major surface of the gate electrode of the MOS transistor is progressed by post-oxidation, thereby to form a gate bird's beak between the gate electrode and the semiconductor substrate. In other words, concentration of electric field at, in particular, both ends of the gate electrode can be suppressed by forming the gate bird's beak. Thus, the high breakdown voltage transistor having a sufficiently high drain breakdown voltage can be achieved. FIG. 15 is a vertically cross-sectional partial view of a semiconductor memory device thus obtained.
As is shown in FIG. 15, this semiconductor memory device has a stacked gate structure. Specifically, in a memory cell array region 50 on a semiconductor substrate 41 formed of a p-type silicon semiconductor substrate, a floating gate 43 and a control gate 45 consisting mainly of polysilicon are stacked with first and second gate insulating films 42 and 44 formed of silicon oxide films, etc. interposed. On the other hand, in a peripheral circuit region 51, a gate electrode 49 consisting mainly of polysilicon is provided in the state in which a third gate insulating film 48 consisting of a silicon oxide film, etc. is interposed between the substrate 41 and the gate electrode 49. Source and drain regions 46 formed of n.sup.+ -diffusion layers are formed in the memory cell array region 50 and peripheral circuit region 51 of the semiconductor substrate 41 on both sides of the gates. A post-oxidation film 47 is provided to cover the entire surface of the substrate 41. In FIG. 15, reference numeral 40 denotes a field oxide film formed selectively in a device isolation region of the semiconductor substrate 41.
In FIG. 15, reference numeral 47a denotes a gate bird's beak formed between the gate electrode 49 and the semiconductor substrate 41. Since the gate bird's beak 47a is formed, as described above, end portions of the gate electrode 49 are rounded and concentration of electric field at both ends of the gate electrode 49 is avoided. Moreover, it is possible to attain a sufficient thickness of the third gate insulating film 48 lying between the gate electrode 49 and semiconductor substrate 41. Thus, the insulation breakdown voltage, e.g. a drain breakdown voltage, of a completed MOS transistor is increased. In this prior art, the gate bird's beak 47a is formed by a heat treatment in an oxidizing atmosphere after the stacked gate structure of the floating gate 43 and control gate 45, the gate electrode 49 and source and drain regions 46 are formed.
When the gate bird's beak 47a is formed by post-oxidation on the MOS transistor in the peripheral circuit region 51, however, a gate bird's beak 47b is also formed at the same time between the floating gate 43 and control gate 45 in the memory cell array region 50. As the formation of the gate bird's beak 47b progresses between the floating gate 43 and control gate 45, the effective thickness of the second gate insulating film 44 lying between the floating gate 43 and control gate 45 increases and the effective area thereof decreases, resulting in an decrease in the capacitance of the second gate insulating film 44. Consequently, the coupling ratio between the capacitance of the second gate insulating film 44 and that of the first gate insulating film 42 decreases. As a result, a necessary voltage to be applied in order to write or erase data in the NAND cell unit increases and a power consumption of the nonvolatile semiconductor memory device may increase. Besides, a higher insulation breakdown voltage may be required for the high breakdown voltage transistor on the peripheral circuit region 51.
As has been described above, in the nonvolatile semiconductor memory device having the stacked gate structure comprising the floating gate and control gate, there is an attempt in the prior art to increase the insulation breakdown voltage of the high breakdown voltage transistor constituting part of the peripheral circuit by forming the gate bird's beak between the gate electrode and the semiconductor substrate by post-oxidation. However, in the prior art, a gate bird's beak is similarly formed in the transistor of the memory cell and a necessary voltage to be applied in order to write or erase data in the memory cell increases.